input output
0-0-0 > 0
0-0-1 > 1
0-1-0 > 1
0-1-1 > 0
1-0-0 > 1
1-0-1 > 0
1-1-0 > 0
1-1-1 > 1
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 module ex (in,q); input [2:0] in; output reg q; always @(in) case (in) 3'b000: q=0; 3'b001: q=1; ... endcase
True in this case. I also agree that it's good if you can recognize the logic behind the table in post #1.yes, your code is right (Behavioural model). But why can't you write it in more simple way.
If you see the logic, it is nothing but Ex-or of all the bits. output is '1' when you have odd no. of 1's in input.
you can simply write an assign statement (don't make q as reg)
assign q = ^in;
The purpose of behavioral coding is however to free you from doing manual logic minimization.
like this?
module ex (in,q);
input [2:0] in;
output reg q;
always @(in)
case (in)
3'b000: q=0;
3'b001: q=1;
...
endcase
I tried simulating on iverilog.com but I got an error when trying to assign q = ^in however the other code worked just fine. I just realized that I can't use a mux because the exercise was strictly about a 3:1 combinational circuit with a,b,c as in and q as out...
Code Verilog - [expand] 1 2 3 4 5 6 7 8 module main; reg [3:0] in = 4'b1011; assign out = ^in; initial begin $display("in = %b, out = %b", in, out); $finish; end endmodule
I tried simulating on iverilog.com but I got an error when trying to assign q = ^in however the other code worked just fine. I just realized that I can't use a mux because the exercise was strictly about a 3:1 combinational circuit with a,b,c as in and q as out...
Anyway... does anyone remember how to solve logic functions based on 2:1 mux?
This is an example I have from class but I just can't figure how to apply it to the above function...
This is my guess:
!A*(!B*C*D + C*!D) + A*(!B*C + !B*!C*!D) + (B*!C*D)
but I don't know if its right and from here I have no idea how to continue... can someone please give me a hint?
Also I have a question to all, is there any way to implement a not gate using 2:1 Mux?
1 --|\
| |--output = not(I)
0 --|/
|
input = I
Yes, very easily........
Code:1 --|\ | |--output = not(I) 0 --|/ | input = I
Is there any way to implement a not gate using only 2:1 Mux (without using supply 1(VCC) or 0(GND)) ?
You are hijacking the OP's thread. If you have your own Q's start your own thread.
You may receive infractions from Moderators for not following the rules.
I actually don't mind... we are all here to learn... having non-sense rules will only hurt the community and I've already been warned for some stuff that made my head hurt... so I decided to just ignore the warnings...
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