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For an efficient utilization of an FPGA,
the vhdl/verilog has to be target FPGA architect dependent.i.e, our code shud infer to the xilinx primitives wherever required.
We know, FPGA has Hard core Multipliers and BlockRAMs modules inside.
for example,assume we want to write an application which requires a large memory module inside.
if our code is not properly written, then this memory logic will be implented using the CLBs itself,
and not using the availabe BlockRAMs.
The way we write the code, will infer what logic has to be utilized inside the FPGAs.
sarah said:Hi,
Have this question, is verilog coding targetted to ASIC is the same if we want to target it to FPGA?
tq in advance.