Verilog coding for ASIC vs FPGA

[sarah]

Hi,
Have this question, is verilog coding targetted to ASIC is the same if we want to target it to FPGA?

tq in advance.

 

[wkong_zhu]

Some must modified like gated clock, generated clock circuit to target to FPGA. memory also different between ASIC and FPGA.

 

[JasonMa]

Nod. I think the most different is memory.
In FPGA design, yan can instantiate the memory module supplied by the FPGA vendor directly.

 

[zyphor]

I think the differences are

1. FPGA are based on LU or other kinds of macro unit & ASIC are based on stand cell.

2. Macroes are different

For the reason above , the coding style must adapt to the tools which would make full use of hardware resource.

 

[nemolee]

I have another consideration different from them. If you are designing ASIC by verilog HDL. And you have to emulate your design through FPGA. You want to verify your design right. You have to keep the same between ASIC and FPGA. Or you can't promise your design is OK. Thus your design must work normally in FPGA and ASIC.

 

[hamadeh]

I think that the "coding" itself will not differ that much... what will differ in your design is the generated output file, it will not be directed to a specific FPGA....

 

[sarath51]

The coding styles in ASIC and FPGA differ with respect to the timing like the implementation of pipe lines , regisering the ouptpust etc

 

[floatgrass]

fsm coding style is different.
make full use of device cell type.

 

[Renjith]

For an efficient utilization of an FPGA,
the vhdl/verilog has to be target FPGA architect dependent.i.e, our code shud infer to the xilinx primitives wherever required.
We know, FPGA has Hard core Multipliers and BlockRAMs modules inside.
for example,assume we want to write an application which requires a large memory module inside.
if our code is not properly written, then this memory logic will be implented using the CLBs itself,
and not using the availabe BlockRAMs.
The way we write the code, will infer what logic has to be utilized inside the FPGAs.

 

[au_sun]

can a macro targetted for an ASIC ,can be implemented in an FPGA,
if there is a problem in tartgetting in fpga ,
what are the things that cause problems?

 

[nand_gates]

One major difference is in FPGA rtl is we can make use of tri state buses
in order to avoid big muxes.

 

[xv_ning999]

I don't consider it as a good idea to use tri state buses in fpga rtl design. It will also cause some unwanted result.

 

[tmdtmd39]

The coding for FPGA have another difference
We had better to use different coding style for different FPGA tools.

 

[andromeda]

If you are doing FPGA prototyping, you could port your RTL or gate-level version of ASIC Verilog files (RTL version is much more common, gate-level porting aprouch is somethimes used by emulation platforms).
When you are porting your RTL to FPGA, you could not do any functional changes, because FPGA verification loose sense.
Two main things which must be changed are memories and clock gating.
Usualy you don't verify clock gating features on FPGA but replaced them with free-running clocks (by removing of PLLs from RTL code) and verify only functionalities not related to clocks turn-on/off.
Memories, depending on size, could be replaced with on-chip block RAMs (or even in LUTs if they are very small) or with off-chip memories (somethimes memory interface is slighty different, so some protocol conversion need to be done).
General rule is: keep behavioral description in your RTL (to be ported for FPGA) for all aritmetic and other logic - * from your RTL could be simple Xilinx built-in hardware multiplier instantiation, but some optimized multiplier implementation need to be implemented with LUT logic.
If your design is to big to fit into biggest FPGA available on the market, you need to partition your design into more then 1 FPGA. There are some 'automatic' partition tools on the market (ie Certify), but in general you could do all this stuff from scripts. If you have a board with more then 1 FPGA, main problem ususally isn't area but number of connections between them - some form of pin time multiplexing usually is used when number of pins isn't enough.

 

[jinruan]

i think coding style depend on the tools.

 

[umairsiddiqui]

For an efficient utilization of an FPGA,
the vhdl/verilog has to be target FPGA architect dependent.i.e, our code shud infer to the xilinx primitives wherever required.
We know, FPGA has Hard core Multipliers and BlockRAMs modules inside.
for example,assume we want to write an application which requires a large memory module inside.
if our code is not properly written, then this memory logic will be implented using the CLBs itself,
and not using the availabe BlockRAMs.
The way we write the code, will infer what logic has to be utilized inside the FPGAs.

what about the portibilty issue, any IP core have to targeted to different vendor library...then he to perform the verification for these different versions (equivalence tests)--- consider the verification overhead

kindly suggest (i.e provide links) books related to fpga/asic portable rtl synthesis and verification techniques

 

[power-twq]

1)in fpga, because each logic cell has a register, so you can use register freely,

but in asic, you should use less registers to save area;

2) in fpga, you must write code in according to architecture of fpga,

but in asic, that's not important.

3) in fpga, you should use less gated clocks, because that's hard to realize in it.

4) in fpga, you can't use too many clocks, because clock resource in fpga is very

limited, but in asic, clock resouce is not a big problem.

Hi,
Have this question, is verilog coding targetted to ASIC is the same if we want to target it to FPGA?

tq in advance.

 

[jjww110]

there are main three diffrence:
1.memory
2.gated clock
3.clock resource