acbalbason
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/= symbol in verilog
hi guys and gals,
does anyone have a tutorial on how to create schematic symbols from a verilog code? and vice versa. that is without the aid of a logic synthesizer. this is for my asic exam. for example a case statement translates to a multiplexer, etc. i want to know the basics and other such cases. thanks!
- al
hi guys and gals,
does anyone have a tutorial on how to create schematic symbols from a verilog code? and vice versa. that is without the aid of a logic synthesizer. this is for my asic exam. for example a case statement translates to a multiplexer, etc. i want to know the basics and other such cases. thanks!
- al