Presently your design has only one max register, min register is causing no design output and will be ignored in synthesis.
max is updated each time din is exceeding the previously stored max value. Obviously, the new value can't be known before din arrives. (There's no known Verilog syntax to accomplish a prophecy, I believe)
So how do you want the design to behave differently? You can e.g. have a separate max_final output register that copies the internal max value when the 1000 samples have been processed. Requiring a respective store input.
Side remark, there should be an asynchronous reset or synchronous init input to initialize the min/max registers.