Synthesis of array types:
A typical synthesizer supports array types of 1D & an array of an array type.
The basic element of an array must be of size 1 bit.
Will synthesize as a Xilinx Block RAM. You can also direct it to synthesize as a distributed RAM or as a register bank by altering the synthesis directive.
I have used this myself many times.
Note that the syntax above is System Verilog, but Verilog 2001 should work the same way.
I want to do the image processing, Array[row][col] of 8 bits then want to process in matrix format. Think if we written the code it will simulate but will not synthesis...