verilog code synthesis

[rvkei11]

Can anyone tell, two dimensional array is synthesisable?

 

[amraldo]

Synthesis of array types:
A typical synthesizer supports array types of 1D & an array of an array type.
The basic element of an array must be of size 1 bit.

Synthesizer support arrays of 1D only and the basic element of the array must be a single bit.

--
Amr Ali

 

[rvkei11]

I think reg [8:0]array[8:0] is synthesisable.... This is eight bit array element...am i right?

 

[amraldo]

It must be an array of array type.
define a new type of reg[8:0] then define the an array of the new type.
It will synthesize.
--
Amr Ali

 

[rvkei11]

Thank you...Can you please tell in verilog reg[8:0]array[8:0][8:0] is synthesisable?

 

[amraldo]

Thats a 2D array, they may not be synthesizable.
1D arrays of anything are for sure synthesizable.
--
Amr Ali

 

[rberek]

2D arrays are defintely synthesizeable with Synplify Pro when synthesizing into Xilinx technology.

for example the following line:

logic                 [(WIDTH-1):0]  mem_block    [(DEPTH-1):0]  /* synthesis syn_ramstyle = "block_ram" */;

Will synthesize as a Xilinx Block RAM. You can also direct it to synthesize as a distributed RAM or as a register bank by altering the synthesis directive.

I have used this myself many times.

Note that the syntax above is System Verilog, but Verilog 2001 should work the same way.



r.b.

 

[rvkei11]

I want to do the image processing, Array[row][col] of 8 bits then want to process in matrix format. Think if we written the code it will simulate but will not synthesis...

 

[kalyansumankv]

2D Array's in Xilinx ISE are synthesizable...
yo can check with even software manuals attached along with ISE for reference