Verilog code help for up_down counter with enable and reset

[LIGHTBUIRN]

Guys i have built an ( up_down counter with enable and reset to reset the counter to zero) using ALDEC HDL and implement it in FPGA
it works but the numbers display in the FPGA are very fast ......

how can I add a control ( call it speed ) that can change the frequencyof the output
If speed =0, then frequency is 2 Hz
If speed=1, then frequency is 20Hz
i studied counter but i have no idea how to change the speed
any help will be appreciated plz .....

 

[Elektronman]

Re: Verilog code help ,,,,؟‏

normally to create a delay, you use an internal counter that increases at every clock tick. Then after a threashold is reached,
you reset this counter and fire the event (up_down counter) or you could check for a particular bit on the counter if you know what you are doing.
Of course getting an exact 2Hz and 20Hz frequency will depend on you setting the proper counter threasholds (this will clearly depend
on your main clock).

 

[LIGHTBUIRN]

Re: Verilog code help ,,,,؟‏

module UpDown(
reset,
enable,
clk,
count
);

input wire clk;
input wire reset;
input wire enable;
output reg [4:0]count;
reg count_state; // 1 => Up; 0 => Down

always @(posedge clk) begin
if (enable == 1 && reset == 0) begin
if (count_state) begin
count = count + 1;
if (count == 15) begin
count_state = 0;
end
end else begin
count = count - 1;
if (count == 0) begin
count_state = 1;
end
end
end else begin
count = 0;
count_state = 1;
end
end
endmodule

This my module how can I do it ???

 

[LIGHTBUIRN]

NO one want to help me with this code ???!

 

[mrflibble]

Generate 20 Hz signal using whatever method you like. When speed=0, divide by 10 more. No I don't have code. The will to type up long replies has been slowly eroded by one-post do-my-homework-for-me's in this forum. No implication intended, just explaining my lack of verbosity.

Also, please use the syntax tags when posting code + consider a testbench.

 

[LIGHTBUIRN]

Guys i am really beginner i didn't studied HDL aldec . we just use it in the lab . when you tell me Generate 20 Hz signal using whatever method you like and divide by 10
( unfortunate i have no idea what you are taking about ) . I only studied counter and if statement . I may understand it if i see the code (change frequency )
also the homework was build an up-down counter using aldec HDL , but the number display in the fbga are fast so I as wondering if I can make them slow like a digital clock
any help will be appreciated

 

[mrflibble]

You can search this forum or do google search for "counter frequency divider verilog". That should get you some example code to read.