Verilog code for sinc3 filter - 2s complement question

[sammyt09]

sinc3 filter

Hi,

I have a brief question relating to some verilog for a sinc3 decimation filter.

In the code, I believe 2s complement is being used for the accumulation process, however, I cant quite understand what is going on. As I do not have a verilog simulator at the moment, I am hoping someone could explain it to me. The relative parts of the code in question is:

-----
/* Definitions */
input mdata1;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;

/* change from a 0 to a -1 for 2's comp */
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
else
ip_data1 <= 1;

/* Accumulation stage */
always @ (posedge mclk1 or posedge reset)

if (reset) begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end

else begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
------------

(Please note, the complete verilog code can be found here: https://www.analog.com/static/imported-files/data_sheets/AD7401A.pdf)

MY QUESTION:
If 2s complement is being used, why is 'ip_data1' defined as either '0' or '1'? I assumed it would have to be either '00....01' or '11....11', i.e plus or minus 1 using 2s complement notation.

If 'ip_data1' is either '0' or '1' the accumulator will surely only accumulate upwards and can never be negative. In which case, it is not 2s complement at all(?!)

If anyone is able to help me in my understanding of this piece of code, I would be extremely grateful. As I say, I do not have a simulator availalable at this stage, otherwise I could have figured this out myself.

Thank you very much in advance!

sammyt09

 

[wade_hassler]

sinc3 filter vhdl

It looks like the code in your post is slightly reformatted wrt the referenced .pdf file:
----------- your post ------------------------
/* change from a 0 to a -1 for 2's comp */
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
else
ip_data1 <= 1;

------- in the .pdf -----------------
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */
else
ip_data1 <= 1;

-------------------------------------
.. apparently you are being advised to edit the Verilog source code if you want to use 2's complement

Wade Hassler

 

[sammyt09]

sinc3

Hi Wade,

Thanks very much for your reply, it is much appreciated. It seems I have simply made an error in my interpretation of this code/comment.

This now makes much more sense and lines up with my original understanding.


Thanks again

sammyt09

 

[FvM]

decimation filter verilog

I don't see, that anything has to be changed to the code, except for the interpretation of the output value. Decimating a one bit input (0..1) results in a positive (straight binary) output coding. By inverting the output MSB, you can turn it into two's complement code.

Generally, in sub and add, there's no difference between signed and unsigned operation, except for the meaning of the bit vectors. This also applies for the CIC decimator as a whole.

 

[sammyt09]

sinc filter verilog

Hi FvM,

Thanks kindly for your reply!

Just to put this in context, I have currently implemented this filter into a VerilogA model. I am using this model in the absence of having an actual Verilog simulator available. So, I suppose, you could say I am using an ideal filter at the moment.

I would like to try and understand the implications of using a real, e.g 24-bit realisation. For example, when will the accumulators saturate? How does the depth of the accumulator affect the result, etc, etc. Essentially, I just want to have a clear picture in my head of how the hardware realisation relates to the ideal realisation.

I understand the basics of decimation and 2s-complement (I think!), but I am still missing something based on your reply ...

If I can understand the operation when the input is an average '0', then I think this will all make sense. For example if the input is an average of zero, then the actual input would be something like "+1, -1, +1, -1" (an equal number of +1s and -1s).

However, as I interpret this code as it is, then surely the accumulators will only ever count up and eventually saturate. I would expect them to count up and down equally and never saturate for an average 0 input. I think what you are saying is that I can get this from interpretting the result differently, but I dont quite understand how?

Is there any chance you could give me a simple example, or point me in the right direction?

Once again, thank you very much for taking the time to look at my question!



Regards

sammyt09

 

[FvM]

sinc 3 filter

Because the input average isn't zero generally, the accumulator will overflow, independent of it's bitwidth. But the input signal level is restored in the diff (comb filter) section of the CIC decimator. There's a lot of literature describing it's operation in detail, starting with Hogenauer's original paper "An Economical Class of Digital Filters for Decimation and Interpolation".

I still don't see to any use of a bipolar +/- 1 input coding. I suggest to use input 0/1 coding and shift the decimator output from 0x0000..0xFFFF to 0x8000..0x7FFF instead, as said.

 

[sammyt09]

average verilog code

Hi FvM,

Once again, thanks very much for your response. It is much appreciated.

I will look into the reference you provided me with and also take note of your suggestion with regards to bipolar +/-1 coding.


Best regards

sammyt09