shashankm8
Newbie level 2
hi all,
we were given a project at college where we have to write a verilog code for cascading 4-bit alu's to form 16-bit alu's.we were comfortable in writing the code for 16 bit alu but it was suddenly changed to cascading of alu's .and my other question is whether to use case statement or if-else statement.And we were also instructed to use clk,rst in the program so that we can perform different instructions when ever the clk is high.And is it possible that we don't use any delays in test bench.
thank you,
we were given a project at college where we have to write a verilog code for cascading 4-bit alu's to form 16-bit alu's.we were comfortable in writing the code for 16 bit alu but it was suddenly changed to cascading of alu's .and my other question is whether to use case statement or if-else statement.And we were also instructed to use clk,rst in the program so that we can perform different instructions when ever the clk is high.And is it possible that we don't use any delays in test bench.
thank you,
