Verilog code error I can't define!

[billkas]

Hello everyone!

I'm a noob in Verilog and I've written this module:

module databus_send(data_out, signature, data_send, data_last);

	output [31:0] data_out;
	output signature;
	
	input [31:0] data_send;
	input [31:0] data_last;
	
	integer i, count;
	
	assign count = 0;
	
	//hamming distance detector
	for (i=0;i<32;i=i+1)
		begin
			if data_send[i]^data_last[i]==1 
				count = count + 1;
		end
	end
	if count > 16
		begin
			signature = 0;
		end
	else
		begin
			signature = 1;
		end
	end
	
	data_out = data_send;
	data_last = data_send;
	
endmodule

What I get is: v(16): Error [...] near "for": syntax error
As far as I can tell, my for loop syntax is ok, what's going on?

Sorry if this post is in the wrong category. I would really appreciate your help!
Thank you! :wink:

 

[FboDigit]

You have too many "end". Try

for (i=0;i<32;i=i+1) begin
if (data_send^data_last==1)
count = count + 1;
end

in verilog each "end" must be linked to a "begin" I see that the rest of your code have too many "end" statements


if count > 16
signature = 0;
else
signature = 1;

This should do the work. You dont need the "Begin" statement when your "if" only have one line.

If you had written something like the following code you must write both "begin" and "end"

if (count > 16) begin
signature = 0;
signature1=0;
end
else begin
signature = 1;
signature1 = 1;
end

Also, always use the () when you use the : if,case...

Hope it help

 

[billkas]

Thank you for the answer! I did exactly what you suggested, but still it won't compile :/

 

[kunaraj]

The coding style is wrong. Don't use this kind of "FOR" loop and you cannot synthesize.
Better change the logic and then try. With the combination of XOR gate and a counter you can achieve this..

 

[shanmugaveld]

For loop is synthesizable only.
for loop, if statements should be within always block.
put "count" also inside always block.
without using assign.
Do this changes along with what "FboDigit" suggested.

 

[billkas]

Thank you very much for your answers, I've found out what the mistake was! I'll post the right one asap!