billkas
Newbie level 3
Hello everyone!
I'm a noob in Verilog and I've written this module:
What I get is: v(16): Error [...] near "for": syntax error
As far as I can tell, my for loop syntax is ok, what's going on?
Sorry if this post is in the wrong category. I would really appreciate your help!
Thank you! :wink:
I'm a noob in Verilog and I've written this module:
Code:
module databus_send(data_out, signature, data_send, data_last);
output [31:0] data_out;
output signature;
input [31:0] data_send;
input [31:0] data_last;
integer i, count;
assign count = 0;
//hamming distance detector
for (i=0;i<32;i=i+1)
begin
if data_send[i]^data_last[i]==1
count = count + 1;
end
end
if count > 16
begin
signature = 0;
end
else
begin
signature = 1;
end
end
data_out = data_send;
data_last = data_send;
endmodule
What I get is: v(16): Error [...] near "for": syntax error
As far as I can tell, my for loop syntax is ok, what's going on?
Sorry if this post is in the wrong category. I would really appreciate your help!
Thank you! :wink: