Verilog Blocking and non-blocking Statements

[flash23]

module blocking(a,b,c);
  output reg a,b;
  input c;
  
  initial 
  begin
  $monitor (",monitor=",a,$time);
    a<= #5 1'b0;
    a<= #10 1'b1;
    
    $strobe ("strobe=",a,$time);
  end
  
  endmodule

The output I'm getting is

run
# ,monitor=x                   0
# strobe=x                   0
# ,monitor=0                   5
# ,monitor=1                  10

WHich according to my understanding should be

run
# ,monitor=x                   0
# strobe=x                   0
# ,monitor=1                  10

As after calculating the RHS of first statement it will go to the next statement. And there it will overwrite the previous assignment scheduled to 'a' of '0'.
I am using questa sim 6.6d.