[SOLVED] Verilog arithmetic shift weird behavior

[jmarcelold]

Pleas some one can explain me why in the below code, x0_eq is not equal to x1_eq?

`timescale 10ns/1ns
module test;
reg signed [8:0] x0, x1, x0_shifted, x0_eq, x1_eq;
initial begin
x0 = -27;
x0_shifted = x0 >>> 3;
x0_eq = x0_shifted + x0[2];

x1 = -27;
x1_eq = (x1 >>> 3) + x1[2];
#10;
$finish;
end
endmodule

 

[er.akhilkumar]

Actually, in first case three times right shift of -27 is calculated which is -4(9'b000111100) and is stored in register of signed type, so it is stored as -4. Then it is added with x0[2] (which is 1) and becomes -3.

But in second case, after the calculation of three right shifts of -27, result is not stored in signed format but it is used in another operation directly so it is used as unsigned decimal(-4 in unsigned decimal is 60), after adding x1[2] it becomes 61. All things are clear except why 61 is not stored in signed format in x1_eq.

Cheers,
Akhil Kumar

 

[jmarcelold]

Akhil,
I think I understood what is happen. The operation a>>>b not only do an arithmetic shift, but it also re-size the variable (I did not know that). This is the reason why -27>>3 is treated as 6'b111100 instead of 9'b111111100, which is what I was expecting. Then, because x1[2] is unsigned, the "+" operation is unsigned, and the result is extended to match the 9 bits as an unsigned value.

Regards

Jose Marcelo L. Duarte