Verilog and VHDL noise modelling

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deep_sea

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Hello guys,
How can I model the noise using Verilog or VHDL?
Are there any examples for the following noise modelling:
White noise
Thermal noise
1/f noise
oscillator noise
 

Your question isn't very specific, what do you want to achieve?

VHDL and Verilog are digital simulators without means to represent analog signals or sources.

I can imagine a discrete noise generator as part of a digital signal processing test bench, it could e.g. use the pseudo random function UNIFORM() in IEEE.MATH_REAL and possibly digital filters for spectral shaping.
 

You are right. But what I want to know, what are the possibilities to represent different types of noise sources using even mixed signal languages like VHDL-AMS, Verilog-A(AMS). To build a system model for example.
 

in theory, verilog/vhdl can be used just like a programming language and you can model anything you want.

i think the real questions is whether these languages are good for this purpose. I would argue that no, they are not. if you need system-level model, matlab is probably a much better fit.
 
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Thanks for your reply. If someone does not have Matlab license, which methodology is suitable in your opinion for system modelling of noise and/or component mismatch? The available tools are Cadence Spectre/AMS
 

if you don't have access to matlab, get octave.

I still don't understand what you actually have as a system and why you insist on using a low level simulator. do you actually have a circuit with a certain topology? what is your application?
 
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