Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog-AMS transition Filter

vleam13

Member level 1
Member level 1
Joined
Mar 3, 2010
Messages
37
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,560
Hi,

I have question on veriloga code.

For transition filter, how can I create output signal with defferent rising edge delay and falling edge delay?
The problem now is transition command cannot used in if-else statement.

Example:
V(out) <+ transition(Vout, Td, Tr, Tf) ;
I need different Td for rising and falling edge.

Thanks.

regards.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top