I'm trying to simulate a simple capacitor module written in Verilog-A as follows:
Code:
`include "disciplines.vams"
`include "constants.vams"
module capacitor_model(p,n);
real q=1.609E-19;
real L=300E-9;
inout p,n;
electrical p,n;
analog begin
I(p,n) <+ (2E9*q*L) * ddt(V(p,n));
// I(p,n) <+ (9.654E-17) * ddt(V(p,n));
end
endmodule
The capacitor has a value calculated with 2E9*q*L. When I use the commented line, i.e. "I(p,n) <+ (9.654E-17) * ddt(V(p,n));", the module acts correctly as a capacitor of that value. However, when I try to make Verilog-A to make the capacitance calculation as 2E9*q*L as the uncommented line "I(p,n) <+ (2E9*q*L) * ddt(V(p,n));", the component does not act as a a capacitor. I think the multiplication 2E9*q*L has error. How can I correct this?
The capacitor model is the model I posted in first post. When I use the line which assigns the value of the capacitor numerically, the delay can be seen. But when I use the line "I(p,n) <+ (2E9*q*L) * ddt(V(p,n));" Verilog-A complier does not give error but the output of the RC circuit does not have any delay. As I understand from zero delay, the capacitor built by the capacitor_model.va model seems to have zero value to HSPICE. Can you please advise something?
Very thanks
Added after 13 minutes:
Hello,
The same problem is in the resistor module in the following:
Code:
// m
`include "disciplines.vams"
module resistor_model(p,n);
real L=300E-9;
real q=1.609E-19;
real h=6.62E-34;
real Lmeanlow=1600E-9;
real Eph=0.2*1.609E-19;
real R0=(h/(4*q*q))*(1+(L/Lmeanlow));
real b=(h/(4*q*Eph));
inout p, n;
electrical p, n;
analog begin
I(p,n) <+ V(p,n)/((h/(4*q*q))*(1+(L/Lmeanlow))+3.1964E4*V(p,n));
end
endmodule
When I use this resistor as connected to a voltage source, the current is calculated as indefinite by SPICE. But when I use this line:
Code:
I(p,n) <+ V(p,n)/(7591+3.1964E4*V(p,n));
the current is sucessfully calculated. Why does the mathematical expressions give error when I use inside Verilog-A modules?