unluerdincer
Newbie level 3

Hi, I am using Verilog-A to generate a three terminal(3 nodes) switch in CADENCE. My Verilog-A file generates the correct IV characteristics that I expect, but when I try to simulate the fan-out(FO) of a device, I realized that Cadence does not capture defined gate capacitance value in Verilog-A. In order to capture the delay difference between a FO4 and FO16, I need to add node capacitance to my verilog-A model.
I have tried defining it as a parameter, but could not make it work in Cadence.
Do you have any suggestions on how I could define my gate capacitance in Verilog, so that Cadence can capture the fan-out?
Thanks
I have tried defining it as a parameter, but could not make it work in Cadence.
Do you have any suggestions on how I could define my gate capacitance in Verilog, so that Cadence can capture the fan-out?
Thanks