Verilog-A Node Capacitance Problem

[unluerdincer]

Hi, I am using Verilog-A to generate a three terminal(3 nodes) switch in CADENCE. My Verilog-A file generates the correct IV characteristics that I expect, but when I try to simulate the fan-out(FO) of a device, I realized that Cadence does not capture defined gate capacitance value in Verilog-A. In order to capture the delay difference between a FO4 and FO16, I need to add node capacitance to my verilog-A model.

I have tried defining it as a parameter, but could not make it work in Cadence.

Do you have any suggestions on how I could define my gate capacitance in Verilog, so that Cadence can capture the fan-out?

Thanks

 

[pavel_adameyko]

Hello, unluerdincer
Have you tried to do smth like I(net1, net2)<+C*ddt(V(net2, gnd)).
Thanks

 

[unluerdincer]

Hello pavel_adameyko,

I am using look up tables to define my IV characteristics, so I do not have "C" in my equations.

I have tried defining cgs like this
(* desc="gate-source capacitance", units="F" *)
real cgs;
but could not make the Cadence simulator to recognize it. I don't know any other way to define gate capacitance. Do you have any suggestions? Thanks

Dincer

---------- Post added at 09:07 ---------- Previous post was at 08:53 ----------

Hello pavel_adameyko,

I am using look up tables to define my IV characteristics, so I do not have "C" in my equations.

I have tried defining cgs like this
(* desc="gate-source capacitance", units="F" *)
real cgs;
but could not make the Cadence simulator to recognize it. I don't know any other way to define gate capacitance. Do you have any suggestions? Thanks

Dincer