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[SOLVED] Verify this bi-di (Verilog)

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Jan 16, 2008
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Verify this IIC SDA/SCL connection (Verilog)


I want to connect the o/p of an IIC master to external SDA and SCL. The o/p of the master IIC block has ports sda_i, sda_o, sda_t_i, and scl_i, scl_o, scl_t_i.

Given below is the connection sketch as I have visualised the connections.


I have written the tri-state logic in Verilog and is given below.

module axi_iic_bi_di 
   // IIC master interface signals
   // data
   input  wire sda_i,   // IIC data in
   output wire sda_o,   // IIC data out
   input  wire sda_t_i, // Data control
   input  wire scl_i,   // IIC clk input
   output wire scl_o,   // IIC clk output
   input wire  scl_t_i, // clock control
   // IIC slave interface signals
   inout wire Sda_io,
   inout wire Scl_io
  assign sda_o = Sda_io;
  assign Sda_io = (sda_t_i == 1'b1) ? sda_i : 1'bz;
  //pullup(Sda_io); // pullup done in TB
  assign scl_o = Scl_io;
  assign Scl_io = (scl_t_i == 1'b1) ? scl_i : 1'bz;
  //pullup(Scl_io); // pullup done in TB

Can anyone confirm if my Verilog code will deliver the functionality required to connect the IIC master to the inout SDA and SCL?

Thanks in advance.

- - - Updated - - -

If the above is not the proper way to implent the SDA and SCL then what should be done?
Use a MUX, with sda_t_i being the output enable (the IIC master spec says that Sda_T is the "serial data o/p enable to 3-state buffer"; same for the Scl)?
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if scl_t_i is an active low tri-state control then it's coded correctly, otherwise if it's tri-state when high then the mux inputs should be swapped.


The scl_t_i (this is an i/p port in my tri-state module) is connected to the output pin SCL_T of the IIC master.

I am giving the following info directly from the IIC master module spec...
The SCL_T is an output port with should have initial state 0x0 and is "IIC Serial Clock Output Enable to 3-state buffer".
But there isn't any info on it being active high or low. I have interpreted it to be active high and have coded accordingly.
What should I do? Is it correct then?

Given the name SCL_T it looks like a active high tri-state (i.e. if the SCL_T is logic 1 the buffer is to be tri-stated)

Most naming conventions would use something like SCL_E, SCL_ENA, SCL_OE etc to mean enable the output (i.e. drive the buffer)
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Given the name SCL_T it looks like a active high tri-state (i.e. if the SCL_T is logic 1 the buffer is to be tri-stated)

You are right ads-ee! I just changed my logic in the 3-state RTL code and can clearly see the SCL and SDA transitions in my simulation. Now I feel relieved! :)

I think one could have also used the Xilinx EDK XPS to generate a 3-state buffer that could be instantiated (verilog example from Bi-Directional IOBUF template in Vivado) with the AXI IIC IP:
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(O), // Buffer output
.IO(IO), // Buffer inout port (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input, high=input, low=output

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