verdi compiling error - mixed vhdl

[billylee]

Hi everyone
I need your help
I have some problem verdi compiling with mixed vlog & vhdl source

my file list
top.v
sub0.v
sub1.v
sub2.v
sub3.v
sub4.vhd
sub4_0.vhd
sub4_1.vhd

so I make flist like this
top.v
sub0.v
sub1.v
sub2.v
sub3.v
sub4.vhd
-vhdl sub4_0.vhd
-vhdl sub4_1.vhd
& verdi -sv -f flist

but this is not work
what can I try next step?

have a goodday!

 

[ljxpjpjljx]

-sv option is the "system verilog" compile option!
vericom is the compiler for the verilog code and vhdlcom is the compiler for the vhdl code!

 

[billylee]

hello ljxpjpjljx
thanks to your reply
but I'm wondering about linking skill for mixed structure not -sv option, -sv option is needless at this source code, sorry for your confusing but thanx a lot