Hi People ,
I am just wondering if this scenario is possible to implement, I have my doubts but its worth a try.
If I have stored all my output data in an array, lets say I have 16 output words:
write_file : PROCESS(clk_in)
FILE f2 :TEXT IS OUT "./codes.txt";
VARIABLE l2 : line;
VARIABLE code : std_logic_vector(3 downto 0);
BEGIN
IF(rising_edge(clk_in)) THEN
code := code_signal;
write(l2,code);
writeline(f2,l2);
END IF;
END PROCESS write_file;
your signal code_signal is a 3 bit signal you intend to write.
Remember it is imp to transfer this signal into a 'variable' before writing into file.
Also, you can include any 'if-then-else' condition in the above code to write down the value conditionally.
Any probs, let me know
Kr,
Avi
This code must go in the entity, where the signal to be written into the file is accessible.
If you dont want to write this code deep inside your design, then you may use
init_signal_spy(a modelsim function) to mirror the signal into top level testbench, and then you can write this code in the top level testbench. But the prob is, 'init_signal_spy' is only availabe if you are using modelsim.