VDHL output data to textfile ?

[suddy72]

Hi People ,
I am just wondering if this scenario is possible to implement, I have my doubts but its worth a try.
If I have stored all my output data in an array, lets say I have 16 output words:

1) 0000
2) 0001
3) 0010
4) 0011
5) 0100
6) 0101
7) 0110
8.) 0111
9) 1000
10) 1001
11) 1010
12) 1011
13) 1100
14) 1101
15) 1110
16) 1111

Is it possible to somehow take these values and output them in a text file on the PC, that way I can then analyse them in Excel or MatLab ?

Any help/code would be appreciated.

Thanks again

Stuart

 

[avimit]

certainly:
Here is the code you need

write_file : PROCESS(clk_in)
FILE f2                       :TEXT IS OUT "./codes.txt";
VARIABLE l2                   : line;
VARIABLE code                 : std_logic_vector(3 downto 0);
BEGIN
  IF(rising_edge(clk_in)) THEN
    code := code_signal;
    write(l2,code);
    writeline(f2,l2);
  END IF;
END PROCESS write_file;

your signal code_signal is a 3 bit signal you intend to write.
Remember it is imp to transfer this signal into a 'variable' before writing into file.
Also, you can include any 'if-then-else' condition in the above code to write down the value conditionally.
Any probs, let me know
Kr,
Avi

http://www.vlsiip.com

 

[suddy72]

thanks mate ,
il have a go at that code.
where about do i attach this code in my design ,
just in the top level code ??

 

[avimit]

This code must go in the entity, where the signal to be written into the file is accessible.
If you dont want to write this code deep inside your design, then you may use
init_signal_spy(a modelsim function) to mirror the signal into top level testbench, and then you can write this code in the top level testbench. But the prob is, 'init_signal_spy' is only availabe if you are using modelsim.

kr,
Avi
http://www.vlsiip.com

 

[suddy72]

Hi mate ,

i put that code in the the file where the output signal is,
but i am getting a lot of errors.

1st being - Undefined symbol 'TEXT'. Should it be: EXT or nEXT?

do i have to alter any of the code you gave me ? i take it code_signal is my output signal ? or am i wrong ?

do i have to decalre anything else or move any of your code about ?

thanks , you have been a real help.

Stuart

 

[avimit]

You havent included textio package. To do that include the following on the top of your code:

USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;

let me know if there are any probs, and I will try to solve them.

 

[suddy72]

hi mate,
That got rid of a lot of errors.
one left ,"Type of code is incompatible with type of address." at the line,code := code_signal;

il PM you my code mate so you can have a look at it , its really simple anyway , all it is doing is sampling data then outputing to memory address.

Il send it to you PM now.

cheers ,

stuart

 

[avimit]

send me ur code, and I will edit it for you.

 

[suddy72]

Hi mate,

I sent it to you via PM.


Did you get it ?

If not do you have e-mail and il send it.