Feb 6, 2013 #1 H hbeck Junior Member level 2 Joined Aug 3, 2011 Messages 21 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,419 I got some problems with my VCS-MX simulation, which massively slows down after running some million cycles. My Setup: SV Testbench VHDL unit under test binded SVAs to some VHDL submodules Compiled with: vcs -debug_pp -sva_bind <bind_file> -assert dumpoff <toplevel> Does anyone knows already about that problem and can give me a hint how to fix it?
I got some problems with my VCS-MX simulation, which massively slows down after running some million cycles. My Setup: SV Testbench VHDL unit under test binded SVAs to some VHDL submodules Compiled with: vcs -debug_pp -sva_bind <bind_file> -assert dumpoff <toplevel> Does anyone knows already about that problem and can give me a hint how to fix it?
Feb 6, 2013 #2 T tariq786 Advanced Member level 2 Joined Feb 24, 2004 Messages 562 Helped 67 Reputation 134 Reaction score 53 Trophy points 1,308 Location USA Activity points 3,048 I believe assertions do slow down the simulation. Are you not expecting this type of behavior?
Feb 7, 2013 #3 H hbeck Junior Member level 2 Joined Aug 3, 2011 Messages 21 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,419 tariq786 said: I believe assertions do slow down the simulation. Are you not expecting this type of behavior? Click to expand... Of course i do expect that behavior, but the simulation speed is getting even more slower over runtime. After some milliseconds simulation time the worst effect is reached with 20ns simulation time per Realtime Second!
tariq786 said: I believe assertions do slow down the simulation. Are you not expecting this type of behavior? Click to expand... Of course i do expect that behavior, but the simulation speed is getting even more slower over runtime. After some milliseconds simulation time the worst effect is reached with 20ns simulation time per Realtime Second!