VCS + SVA simulation slows down

[hbeck]

I got some problems with my VCS-MX simulation, which massively slows down after running some million cycles. My Setup:

• SV Testbench
• VHDL unit under test
• binded SVAs to some VHDL submodules

Compiled with: vcs -debug_pp -sva_bind <bind_file> -assert dumpoff <toplevel>

Does anyone knows already about that problem and can give me a hint how to fix it?

 

[tariq786]

I believe assertions do slow down the simulation. Are you not expecting this type of behavior?

 

[hbeck]

I believe assertions do slow down the simulation. Are you not expecting this type of behavior?

Of course i do expect that behavior, but the simulation speed is getting even more slower over runtime. After some milliseconds simulation time the worst effect is reached with 20ns simulation time per Realtime Second!