hi..
me tried to implement one of my verilog code in synopsys. but in VCS tool itself when me pressed run option to get simulation waveforms it continous to run and after some time got following message:
A 32 bit version can handle maximum 2^32 bit (4GB) memory. It seems memory requirement during simulation crossed the 4GB limit. To address memory more than 4GB you require a 64 bit version.
A 32 bit version can handle maximum 2^32 bit (4GB) memory. It seems memory requirement during simulation crossed the 4GB limit. To address memory more than 4GB you require a 64 bit version.
May be some problems exist in your RTL or testbench.
For example, $finish is never achived so it causes "infinite" time to complete simulation).
Code:
// tb.v
reg a;
// initial block with stimulas
initial begin
a = 1; // forever 1
wait(a == 0); // this event will never occur, but the simulator will wait.... and eat memory I think
$finish;
end