nc-verilog gate sim
Hi all,
In my opinion, for the small design (less then 10k) that in the RTL code simulation, you could not see much different from the simulation tools.
However for the large design that in the gate-level simulation, NC-verilog and VCS are fast enough to simulate the result, but Modelsim is quite slow. There is one good thing by using Modelsim which is it can run mix-hdl, but I do not care, since i'm only using verilog for most of my design.
Regards,
always_smart