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VCD file generation in VHDL

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muni123

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vcd files generation

Hi all,
Can anybody provide me information on creation of .vcd file in VHDL testbench
I need commands we use and where to keep those commands inside the testbench.
similar to the $dumpfile() in Verilog testbench...

Thanks & Regards
 

hys

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It also depends on the simulator whether it supports VCD file dumps...
In case of Mentor's modelsim, it has some commands like
- vcd file
- vcd add <signal_name>
These commands can be used to get vcd dumps of the chosen signals..

Best Regards,
Harish
 

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