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varying the wire/assignment delay

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sainiparvesh

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inurl:viewtopic wire

Hi,
I want to vary the delay between ref_clk and sample_ref_clk upon accurance of stop_clk's posedge with following code :
// stop_clk is a clock having frequency much smaller than clock ref_clk

always @ ( posedge stop_clk )
begin
sample_delay = sample_delay +5 ;
end

assign # sample_delay sample_ref_clk = ref_clk ;

But I am not getting delay between ref_clk and sample_ref_clk in my vcd dump.

Regards,
Parvesh
 

theertsa

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Delay between ref_clk and sample_ref_clk upon accurance of stop_clk's posedge will be surely shown in any of the written disk id not the its sure that it is corrupted.
 

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