I am developing on digital function generator abt audio. So, the user can select the sampling rate of the waveform from the range 8k to 216kHz in the GUI.
So, the external clk(pll) will be tuned to give the frequency of clock to fpga from the range 95MHz to 105MHz. I am thinking on using reconfig pll in the fpga to give the frequency of 8k to 216k on the fly if possible.
However, i am not yet to the state. I am trying to do timing simulation for the wavefrom(e.g sine wave). I have no idea on how to write the sdc file.
any idea?
thanks