Variable Frequency of clock

[woeichee]

i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz.

My question are:
1. How to write the sdc?
2. Other than sdc, is there any thing(circuit, etc) need to be take care or add in?

thanks

 

[Maxwell077]

Please give a detailed description..
For what purpose, when do you need to change....

Ilgaz

 

[woeichee]

I am developing on digital function generator abt audio. So, the user can select the sampling rate of the waveform from the range 8k to 216kHz in the GUI.

So, the external clk(pll) will be tuned to give the frequency of clock to fpga from the range 95MHz to 105MHz. I am thinking on using reconfig pll in the fpga to give the frequency of 8k to 216k on the fly if possible.

However, i am not yet to the state. I am trying to do timing simulation for the wavefrom(e.g sine wave). I have no idea on how to write the sdc file.

any idea?

thanks

 

[mersault]

let me clarify the problem...

you want a clock in the range of 8kHz and 216kHz.
what will be the step in that range? (1kHz, 10 Khz, etc)

what kind of fpga do you have?
what is the frecuency of the input clock, I mean the fpga's clock?

greetings

 

[xtcx]

Hi friend!, You cannot use Onchip PLL(DCM) at such low range frequency....Maybe you can try DDS core to generate such freqs....Correct me if I'm wrong