Nov 22, 2011 #1 A avishek_sinha_roy Junior Member level 1 Joined Oct 20, 2011 Messages 15 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,402 i am designing a nand, nor, etc logic circuits(mosfet) using cadence @ 32nm technology.what should be the appropriate capacitive load that i have to use corresponding to fan out of 1?..............please give some links to read about this
i am designing a nand, nor, etc logic circuits(mosfet) using cadence @ 32nm technology.what should be the appropriate capacitive load that i have to use corresponding to fan out of 1?..............please give some links to read about this
Nov 22, 2011 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 Get an idea from the cg values in this PTM Low Power 32nm Metal Gate model .