Va modelling during synthesis in Sigexplorer

Status
Not open for further replies.

nikhil

Member level 1
Joined
Feb 23, 2005
Messages
32
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,288
Activity points
1,537
can any one help me in find out the way for via modelling in sigxplorer of cadenec during pre synthesis

nikhil
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…