I've seen many standard cell libraries offering both
positive and negative edge clocked flip-flops. The
setup time and the hold time both pertain to the
active clock edge. If you have enough clock period
(and duty cycle consistency) to accommodate
these keepout times and any intermediate (logic
prop) delays there's no reason you can't clock on
both edges even inside a single logic block. But
the timing analysis is probably on you, and maybe
synthesis tools aren't supportive (I only do hand
wired logic, still, and only am called upon to do it
when synthesis based, standard cell library approach
can't make it).