meir
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I'm trying to run command: vcs -sverilog -f filelist
but I get the error : No source file given.
When I run the same command but with a file list of only verilog files
it compiles succesfully.
what am I doing wrong ?
Thanks
but I get the error : No source file given.
When I run the same command but with a file list of only verilog files
it compiles succesfully.
what am I doing wrong ?
Thanks