link-library=target_library=sc-cadence.db)---- depends on the tool
read-f VHDL.rtl/arbiter.vhd--------- Depends if u use verilog
set_port_is pad
insert pads
verilog out_single
-bit=true
write-f verilog-output gste/arbiter op.v
quit
Modify your RTL and insert pads there and link the library. That is more better and effective way as u dont wanna optimize it, rather for constraining and analyzing the design