#### moein0114

##### Newbie level 6

hi , i am using verilog code to fix the 12 bit input data .

in my module number will be counted before this module and is an input .

i want to change the bit number of main_data ( main_data[number]) , because this bit is wrong so it should be toggled ,

but when its okeii , with every clk this bit changes and i dont want this to happen . i want when main_data[number] has toggled in next posedge clk , it does't happen again .

can any one help me how to do it please ??

in my module number will be counted before this module and is an input .

i want to change the bit number of main_data ( main_data[number]) , because this bit is wrong so it should be toggled ,

but when its okeii , with every clk this bit changes and i dont want this to happen . i want when main_data[number] has toggled in next posedge clk , it does't happen again .

can any one help me how to do it please ??

Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 module fixer (main_data,number,fixed_data,clk); input [12:1] main_data; input clk ; input [3:0] number; output [12:1] fixed_data; reg [12:1]r ; reg [3:0] n ; reg stop = 1'b1 ; always @ ( posedge clk ) begin if ( number != n) stop<=1; if (stop) begin r<=main_data; n<= number ; case (number) 4'b0001 : begin r[1]<=(~r[1]); stop<=0; end 4'b0010 : begin r[2]<=(~r[2]); stop<=0;end 4'b0011 : begin r[3]<=(~r[3]); stop<=0;end 4'b0100 :begin r[4]<=(~r[4]); stop<=0;end 4'b0101 :begin r[5]<=(~r[5]);stop<=0;end 4'b0110 :begin r[6]<=(~r[6]);stop<=0;end 4'b0111 :begin r[7]<=(~r[7]);stop<=0;end 4'b1000 :begin r[8]<=(~r[8]);stop<=0;end 4'b1001 :begin r[9]<=(~r[9]);stop<=0;end 4'b1010 :begin r[10]<=(~r[10]);stop<=0;end 4'b1011 :begin r[11]<=(~r[11]);stop<=0;end 4'b1100 :begin r[12]<=(~r[12]); stop<=0; end endcase end end assign fixed_data=r; endmodule

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