Using generate in another generate

[masoud.malekzadeh]

HI , is it possible to use a generate statement inside another generate statement ?

here is my code but my pre1 and pre2 types are undefined .

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Code VHDL - [expand]
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gen15:for j in 1 to 7 generate 
gen12:for i in 0 to 7 generate 
 
s74:multiplier port map (a =>z1(i),b=>ww1(j-1),clk => clk,result =>pre1(i));   ------- 
s75:multiplier port map (a =>z2(i),b=>ww2(j-1),clk => clk,result =>pre2(i));   -------
s76:adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
s82:multiplier port map (a =>ww1(j-1),b=>three,clk => clk,result =>nww1(j-1));
end generate ;
 
gen13:for i in 0 to 3 generate 
s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
end generate ;
 
gen14:for i in 0 to 1 generate 
s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
end generate ;
 
 
s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(j));
s84:subtractor port map (a =>pre9(j),b=>nww1(j-1),clk => clk,result =>ww1(j));
 
 
end generate;

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[K-J]

HI , is it possible to use a generate statement inside another generate statement ?

Yes.

here is my code but my pre1 and pre2 types are undefined.

Without the full code, it is not really possible to spot the error, but I do note that you don't have an 'end generate' for the outermost generate statement.

Kevin Jennings

 

[xtcx]

I feel generate inside generate will increase more confusion and make the code look untidy....

 

[masoud.malekzadeh]

I want to design a processor that one part of which should be like this

W(k)=Pre_W(k)-3*W(k-1)
pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7

and my arithmetic operations is floating point i should port map them using components .

thanks .

 

[TrickyDicky]

was that a question?

 

[masoud.malekzadeh]

was that a question?

yes , i'm so confused about it .

 

[masoud.malekzadeh]

I feel generate inside generate will increase more confusion and make the code look untidy....

Then what should i do in order to repeat the generate for several times ,?
if after finishing the generate one signal changes the generate will run again ? for example the generate belows finishes for the first time if i update D(i) , the generate will start again ?

for .... generate

x(i)<=D(i)
.
.
end generate .

 

[masoud.malekzadeh]

s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
s76:     adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
s82:multiplier port map (a =>w1(0),b=>three,clk => clk,result =>nw1(0));
end generate ;

gen13:for i in 0 to 3 generate 
s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
end generate ;

gen14:for i in 0 to 1 generate 
s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
end generate ;

--
s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(0));
s84:subtractor port map (a =>pre9(0),b=>nw1(0),clk => clk,result =>w1(1));

In this code i implemented the algorithm that computes only W(1) and the result is ok but to go further W(2),W(3),..... I'm confused ....

 

[xtcx]

Add a generate statement on top of this with 3 index values. What is the problem in doing so?...

 

[masoud.malekzadeh]

Add a generate statement on top of this with 3 index values. What is the problem in doing so?...

by doing that my code is like this

for j in  0 to 7 generate 
for i in  0 to 7 generate 
s74:multiplier port map (a =>z1(i),b=>w1(j),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(j),clk => clk,result =>pre2(i));
s76:     adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
s82:multiplier port map (a =>w1(j),b=>three,clk => clk,result =>nw1(j));
end generate ;

gen13:for i in 0 to 3 generate 
s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
end generate ;

gen14:for i in 0 to 1 generate 
s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
end generate ;

--
s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(j));
s84:subtractor port map (a =>pre9(j),b=>nw1(j),clk => clk,result =>w1(j+1));

end generate ;
end generate ;
Doing so my pre1 and pre2,pre3,pre4 go undefined .