masoud.malekzadeh
Member level 1
HI , is it possible to use a generate statement inside another generate statement ?
here is my code but my pre1 and pre2 types are undefined .
here is my code but my pre1 and pre2 types are undefined .
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 gen15:for j in 1 to 7 generate gen12:for i in 0 to 7 generate s74:multiplier port map (a =>z1(i),b=>ww1(j-1),clk => clk,result =>pre1(i)); ------- s75:multiplier port map (a =>z2(i),b=>ww2(j-1),clk => clk,result =>pre2(i)); ------- s76:adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i)); s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i)); s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i)); s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i)); s82:multiplier port map (a =>ww1(j-1),b=>three,clk => clk,result =>nww1(j-1)); end generate ; gen13:for i in 0 to 3 generate s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i)); end generate ; gen14:for i in 0 to 1 generate s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i)); end generate ; s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(j)); s84:subtractor port map (a =>pre9(j),b=>nww1(j-1),clk => clk,result =>ww1(j)); end generate;
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