Using generate and for loop to index signal name

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stanford

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Say I have inputs as follows:

Code: 
input in0;
input in1;
input in2;
input in3;
...
and what I want to do in generate for loop is something like this.
Code: 
b[0] = in0;
b[1] = in1;
b[2] = in2;
... and so on.

The problem is I cant index the inputs using the variable 'i' in the generate for loop. How can I do this easily with a for loop?
Note: I don't want to use in[N-1:0], I want to keep them as in0, in1...

Code: 
for (i = 0; i < N; i = i + 1)
  b[i] = ?
 

You cannot iterate over identifier names. The best you could do is

wire in[N-1:0] = {..., in3,in2,in1,in0};

In SystemVerilog, this can be simplified as
alias in = {..., in3,in2,in1,in0};
 

In my case, I would make the input as multi_bit, and divide them in the always block inside module.

Code: 
module top(
    input [4:0] in_data,
    input clk,
    input rst_n,
    output valid
)
reg b[4:0];
integer idx;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        for(idx=0 ; idx < 5 ; idx=idx+1)begin
            b[idx] <= 0;
        end
    end
    else begin
        for(idx=0 ; idx < 5 ; idx=idx+1)begin
            b[idx] <= in_data[idx];
        end
    end
end
 

For what its worth macros can manipulate signal names using ``. See how this creates two signals based on the string passed as "OUT". You could unroll your generate loop and replace it with one line macros.

Code: 
`define SYNC(CLK_EN, IN, OUT, INVERT, DFLT)\
	wire OUT, ``OUT``_posedge, ``OUT``_negedge;\
 


Do you compete in Verilog obfuscation competitions?

Stuff like this is going to reduce maintainability, which to me is far more important than trying to avoid typing something out explicitly.

I only use for loops if I've already code everything else with parametrized widths and loop counts. Having a fixed number of inputs like the OP's first post would require a fixed loop count and I would avoid the loop altogether and just use what dave_59 suggested in post #2.
 

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