Hi,
I will be using design compiler to synthesize design. My design contains `ifdef-`endif blocks. I can compile and simulate it using synopsys vcs as:
Code:
vcs +define+<one of possible value for `ifdef> filename.v
That would compile and simulate but I can't seem to find how to synthesize it the same way?
You can create one file consists all parameters and then include that file inside the RTL file. For example you have parameter GATED_CLK and WIDTH_CH , define in one file named test_def.v as follow:
`define GATED_CLK
`define WIDTH_CH
you have to include above file inside your RTL file , for example your RTL file is test.v. Add following line inside the test.v:
`include "test_def.v"
module test (in, out);
----
--
------
endmodule