Dec 19, 2008 #1 X xrisas1 Newbie level 3 Joined Mar 16, 2006 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,299 Hi People, I need to use clock as data but I know that this will give problems after synthesis. What I actually need is to drive a signal only on the positive phase of the clock so I am currently using : data_out <= data_reg when (clk = '1') else (others => '0'); where data_reg is a registered value. Does anybody know a clean solution for that? Thanks
Hi People, I need to use clock as data but I know that this will give problems after synthesis. What I actually need is to drive a signal only on the positive phase of the clock so I am currently using : data_out <= data_reg when (clk = '1') else (others => '0'); where data_reg is a registered value. Does anybody know a clean solution for that? Thanks
Dec 20, 2008 #2 N Nir Dahan Member level 4 Joined May 19, 2008 Messages 74 Helped 15 Reputation 30 Reaction score 8 Trophy points 1,288 Location Munich, Germany Activity points 1,753 Please try reading this: https://asicdigitaldesign.wordpress.com/2007/08/09/driving-a-clock-frequency-signal-from-a-register/ maybe it will help you. It describes a way to drive clock frequency signal without having the clock in the data path. ND. https://asicdigitaldesign.wordpress.com
Please try reading this: https://asicdigitaldesign.wordpress.com/2007/08/09/driving-a-clock-frequency-signal-from-a-register/ maybe it will help you. It describes a way to drive clock frequency signal without having the clock in the data path. ND. https://asicdigitaldesign.wordpress.com