Using clock as data - Drive a signal only on +ve clock phase

[xrisas1]

Hi People,

I need to use clock as data but I know that this will give problems after synthesis.
What I actually need is to drive a signal only on the positive phase of the clock so I am currently using :

data_out <= data_reg when (clk = '1') else (others => '0');

where data_reg is a registered value. Does anybody know a clean solution for that?

Thanks

 

[Nir Dahan]

Please try reading this:
https://asicdigitaldesign.wordpress.com/2007/08/09/driving-a-clock-frequency-signal-from-a-register/
maybe it will help you.
It describes a way to drive clock frequency signal without having the clock in the data path.

ND.

https://asicdigitaldesign.wordpress.com