Using CE of SRL - need help with the code

module led_counter(clk,led_out, rst);

input clk, rst;
output reg [3:0] led_out;

wire clk_buf;

assign one = 1'b1;
assign zero = 1'b0;

wire [6:0] clk_en;

////////////BUFG INSTANTIATION/////////////////////
 
BUFG BUFG_1 (
      .O(clk_buf),     // Clock buffer output
      .I(clk)          // Clock buffer input
   );
//////////////////////////////////////////////////



// Input clock of 16 Mhz
// Divide by 16

SRLC16E #(.INIT(16'h0001))                   // Initial Value of Shift Register
           SRLC16E_1 (       
                      .Q(),                  // SRL data output
                      .Q15(clk_en[0]),       // Carry output (connect to next SRL)
                      .A0(one),              // Select[0] input
                      .A1(one),              // Select[1] input
                      .A2(one),              // Select[2] input
                      .A3(one),              // Select[3] input
                      .CE(one),              // Clock enable input
                      .CLK(clk_buf),         // Clock input
                      .D(clk_en[0])          // SRL data input
                     );


genvar i;

generate
    for (i=0; i < 6; i=i+1) 
    begin: gen_10_srl
      // Divide by 16 x 10^6 = 16 Mhz/16_000_000  = 1Hz
      SRLC16E #(.INIT(16'h0001))                   // Initial Value of Shift Register
                 SRLC16E_2 (       
                            .Q(clk_en[i+1]),       // SRL data output
                            .Q15(),                // Carry output (connect to next SRL)
                            .A0(one),              // Select[0] input
                            .A1(zero),             // Select[1] input
                            .A2(zero),             // Select[2] input
                            .A3(one),              // Select[3] input
                            .CE(one),              // Clock enable input
                            .CLK(clk_en[i]),       // Clock input
                            .D(clk_en[i+1])        // SRL data input
                           );
    end
endgenerate


reg clk_1s_d;

always @(posedge clk_buf)
  clk_1s_d    <= clk_en[6];
  

assign clk_1s = clk_en[6] & (~clk_1s_d);

always @(posedge clk_buf or posedge rst) begin
 if(rst == 1'b1)
  led_out   <= 4'b1110; 
 else if (clk_1s == 1'b1) begin
   case (led_out)
     4'b0111 : led_out <= 4'b1110;
     4'b1110 : led_out <= 4'b1101;
     4'b1101 : led_out <= 4'b1011;
     4'b1011 : led_out <= 4'b0111;
   endcase
 end
end
 
endmodule