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Use of ASITIC inductor Lauout in LNA circuit simulation and layout in Cadence

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kapil86

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I have extracted PI model parasitics of inductor in ASITIC and imported CIF file in Cadence. It is visible in cadence layout window.
How to use this layout of inductor in my LNA (low noise amplifier) circuit and layout for Schematic and DRC ,LVS respectively. Please help me its very urgent for me. waiting for solutions.

Thank you
 

fanshuo

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built the PI model with ideal R,C,L
you can simulate it
but it is impossible to DRC and LVS
 

kapil86

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Dear fanshuo,
Thank you to reply, the Schematic simulation i will do using ideal R,L,C. but how to verify my Schematic simulation results to post layout simulation its also necessary at high frequencies.
 

fanshuo

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By using ASITIC, you should have all the parasitics of the inductor alone
but you can not simulate it with the rest of the circuit for post layout simulation
i do not think it is possible
 

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