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Use generic to design a ASIC dos'nt poses a problems of synthesis?

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omar-malek

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Hi to all
i have a queqtion about asic syntèesis
now i am in my final year project i want to design a digital filter fir channel selection
so i want to use generic vhdl module but i don't know if crea a probleme after when i passe to the step of synthèsis using synopsys.
 

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