USB Host Simulation Model

[ansonng913]

usb simulation model

Hi,
I have a softcore of USB controller. I want to do a simulation using Cadence NC Verilog. I would like to know whether there is a USB host model, for example written by Verilog, for simulation.

Thank you very much for your help!

Anson

 

[pamulurureddy]

Yes there will be host model. i was working on c language host model and for simulation i use to write PLI routines

Reddy

 

[lychee]

Could U please share your C language model

 

[Ansunamu]

yes ! please share it