USB Host Simulation Model

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ansonng913

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usb simulation model

Hi,
I have a softcore of USB controller. I want to do a simulation using Cadence NC Verilog. I would like to know whether there is a USB host model, for example written by Verilog, for simulation.

Thank you very much for your help!

Anson
 

Yes there will be host model. i was working on c language host model and for simulation i use to write PLI routines

Reddy
 

Could U please share your C language model
 

yes ! please share it
 

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