Seriously jt_eaton, I made multiple designs with both edges with no issue, the synthesis take care of that properly.
And regarding your simulation "issue", the clock is used on the edge, so inactive state means nothing for a flop!?
Only the asynchronous reset could be care to be disable synchronously on the opposite edge of the edge of the flop, to have the 1/2 period of timing marging between the reset transition and the clock edge.
Beside that, synthesis, scan insertion, clock tree tools handle without any issues a design with has both edge used, included the path which have mix edges has input to output.