Usage of posedge and negedge flip flops in same design

[Goran Dakov]

Is it OK to use both positive and negative edge flip flops on the same clock in the same design from perspective of place & route tools? Is it going to make timing analysis impossible?
Note that it won't have combinational logic depending on the outputs of both a posedge and a negedge sensitive flop at the same time.

 

[barry]

The tools should take care of the timing.

 

[jt_eaton]

Is it OK to use both positive and negative edge flip flops on the same clock in the same design from perspective of place & route tools? Is it going to make timing analysis impossible?
Note that it won't have combinational logic depending on the outputs of both a posedge and a negedge sensitive flop at the same time.

Don't do this, it can create a simulation/synthesys mismatch.

When you start a simulation you must force all clocks into their inactive state. If you have both types then one of them will be forced into their active state and will clock at the start of your simulation. If that clock is generated from a flipflop then it may or may not clock based on the power up value of that flop.

When you get silicon back you may find that some parts work, some parts fail and some parts can be made to pass or fail by chaning voltage and temperature.

Create two clocks for rising and falling edges. Run both in rising edge flipflops and reset both to 0 at the start of your simulation.

 

[rca]

Don't do this, it can create a simulation/synthesys mismatch.

When you start a simulation you must force all clocks into their inactive state. If you have both types then one of them will be forced into their active state and will clock at the start of your simulation. If that clock is generated from a flipflop then it may or may not clock based on the power up value of that flop.

When you get silicon back you may find that some parts work, some parts fail and some parts can be made to pass or fail by chaning voltage and temperature.

Create two clocks for rising and falling edges. Run both in rising edge flipflops and reset both to 0 at the start of your simulation.

Seriously jt_eaton, I made multiple designs with both edges with no issue, the synthesis take care of that properly.
And regarding your simulation "issue", the clock is used on the edge, so inactive state means nothing for a flop!?
Only the asynchronous reset could be care to be disable synchronously on the opposite edge of the edge of the flop, to have the 1/2 period of timing marging between the reset transition and the clock edge.
Beside that, synthesis, scan insertion, clock tree tools handle without any issues a design with has both edge used, included the path which have mix edges has input to output.

 

[jt_eaton]

Seriously jt_eaton, I made multiple designs with both edges with no issue, the synthesis take care of that properly.
And regarding your simulation "issue", the clock is used on the edge, so inactive state means nothing for a flop!?
Only the asynchronous reset could be care to be disable synchronously on the opposite edge of the edge of the flop, to have the 1/2 period of timing marging between the reset transition and the clock edge.
Beside that, synthesis, scan insertion, clock tree tools handle without any issues a design with has both edge used, included the path which have mix edges has input to output.

All flipflops are set to X at the start of a simulation and you must reset them into a known state. If your clock divider flop goes from X->0 at the start of the simulation then a posedge flop will ignore it but a negedge flop will clock at that time. When you get silicon back if that flop powers up in a 1 state then it will reset to 0 and match your simulation. If it powers up 0 then the negedge flop will not clock and your silicon no longer matches the simulation.

This can create a very nasty pvt issue with silicon.

Asynchronous resets will prevent this but you can't always use them.

 

[FvM]

In other words, you are talking about a specific problem that has been observed in your ASIC design flow. It won't occur in ASIC designs with asynchronous reset, neither in usual FPGA hardware that has defined POR state of all FFs.

Thanks for clarifying!